Other Equipment - Development of

Chemical-mechanical polishing is a rapidly emerging industry. As integrated circuit geometries shrink and circuits become more compact, multilevel layering of metal and dielectric films becomes necessary. Unfor­tunately, the topography created by the first film levels often make upper film levels uneven, especially when three or more layers are applied. Current day limits of process equipment technology are truced by multilayer metal CMOS structures. Lithog­raphy, etch and deposition fight each other as device topology variations grow. Surface planarity deteriorates rapidly once an oxide covers the first metal. Attempts to plana­rize oxides with an etchback have met with only limited success. A flat surface is criti­cal for circuit performance. To compensate for this topography, chemical mechanical polishing (CMP) is used. To date, CMP is the most effective means of achieving glob­ally uniform planar wafer surfaces for three or more film layers. CMP involves the use of mechanical pad polishing systems with a polishing slurry. Planarization of the metal and dielectric layers in these advanced devices is essential because the depth-of­field of lithographic equipment is not good enough to compensate for even small bumps, rises, or depressions on the wafer. Lithography has hard limits in its depth-of­focus. Current generation equipment can achieve submicron levels. So, surface flat­ness conditions are critical to achieving higher yields and device speeds. To make sufficiently fine lines, the beam needs a completely flat surface. To date, CMP is the best way to achieve flat wafers.