Multi-Pattern Lithography Economics and Killer Defect Economics

Time Period :2010'sRelevant Date :2010-02-05

Summary : Also known as DPT, or dual pattern technology, for exposing semiconductor wafers was stuck around 2010 because the CoO cost model led to a conclusion that DPT was too expensive. It was really a misapplication of CoO and better tools were needed. Going back to basics: MPT cost analysis needed to start with...

Click here to view full screen

Did EUV development cos ...

14 Jan 2010

Factoids from the edge: Some like to say that EUV development has cost more than ... ... See more

Are the foundries slowi ...

18 Jan 2013

Silicon mythology has it that node progression is predictable and constant. In r ... ... See more

Applied Materials' Prod ...

04 Jul 1998

The Chip Insider's review of Applied Materials' Producer at its introduction ... See more

Maskless Lithography: C ...

10 Nov 1977

IBM’s EL-1: a milestone in e-beam lithography ... See more

Lam Research AutoEtch 4 ...

15 Jul 1981

Lam Research’s AutoEtch 480 was a landmark in the history of plasma etchers. ... ... See more

Megafabs: Why they buil ...

17 Jan 2008

One of the most interesting questions to answer is why are Megafabs so popular? ... ... See more

300mm Semiconductor Waf ...

22 Jul 1998

The industry's transition to 300mm Semiconductor Wafers almost stalled in 1998, ... ... See more

VLSI - An Economist's V ...

15 Jan 1980

A Presentation Draft of The First Wafer Fab Cost Optimization Model1980 ... See more

1983 The Quality Revolu ...

13 Jun 1983

In 1983 the semiconductor equipment industry was coming out of a two-year slow-d ... ... See more

Making Silicon Commerci ...

15 Jun 1955

SEMI's Great Moments in Semiconductor History: In the mid-1950s. Dr. Henry W. Gu ... ... See more