September 22, 1998:
Taiwan is shifting from being a cost leader to a service and technology leader. TSMC and UMC have started to license IP in a move to capture the SOC market. They see SOC from IDMs (Integrated Device Manufacturers) as a huge threat to their markets. But they also think they are in a strong position to capitalize on SOC. First, in serving the fabless chip makers they have access to some of the best designers in the world. Second, they know how to bring designs in from different companies; integrate them into an existing process; and then develop tests that correlate to the process better than anyone in the world.
In flash memory, Macronix has dozens of patents and patents pending. It claims to have developed a new cell that has all the scalability of nand gate cells, while offering the performance of a nor gate cell.
Best-of-Breed: One company in Taiwan has been hitting entitled yields in one month from start-up. The key to this success is extensive linking of inspection and test data into a computer network that automatically downloads process parameters to tools on the line. Engineers can adjust tools as they drift without stepping foot into the fab. Test data is becoming more important than in the past because it can now direct inspection tools directly to where a fault occurred to find the exact cause. This allows positive identification of killer defects, so engineers can ignore the more benign ones.
Japan got the jump on the United States in the eighties by focusing on cleanroom techniques to prevent defects thereby improve yield. Korea got the jump on Japan by using KLA’s yield management methods to identify the remaining defect sources. Could this approach be the way that Taiwan gets the jump on the world? If so, Electroglas could be sitting on a gold mine.
Worst-of-Breed: Some companies in Taiwan are using as much as 40% of their capacity to run test wafers as they try to get a handle on yields in the start-up phase. The typical is 25%.
Cycle Time versus Utilization in Taiwan
8 weeks 100%
7 weeks 90%
6 weeks 80%
4 weeks 70%
Embedded test is in. So, you can toss BIST from your vocabulary. The difference? BIST throws more logic on the chip next to the gates to enable the tester. With SOC, this is impossible as IP drop-ins form impenetrable islands on the chip. Embedded test surrounds these islands with on-chip testers. Does it eliminate test? No. Does it change test? Irrevocably. How? We don’t know. We do know that for twenty years or so, the industry has been side stepping the issue of how to test big chips. SOC will force it to find new ways address the problem. SOC is a top priority for most chip industry executives today and they say test is the number one issue. Right now, LTX’s Fusion system appears closest to addressing these needs.