BEOL Origins | The Chip History Center

This historic report explains Back End of the Line wafer processing when it was new and emergent as a critical part of the semiconductor production process it created entirely new markets for equipment and materials. BEOL was the physical embodiment of a chip maker's IP. State-of-the-art was still planar CMOS with only 1 or 2 metal layers. CMP was just beginning to be applied. 256-megabit DRAM technology was just over the horizon. The industry was focused on how to make lo-K dielectrics and copper interconnect schemes work. Presentations: A BEOL intensive circuit. DRAM cell structures. BEOL vs FEOL. First metal film stack materials and processes for 0.35 and 0.25 micron nodes. Film stacks after first metal. How Resistivity and Permittivity Affect Device Speed. IMD Dielectric film alternatives. Fluorine Lowers Permittivity. CVD vs PVD. Evolution of sputtering techniques for plug filling. BEOL term and word definitions.