The State of Process Development at Intel-32nm, 22nm, 15nm, Defect Densities, Hi-K, Strained Silicon

Summary : Mark Bohr: Senior Fellow and Director of Process Architecture & Integration, Intel: The State of Process Development at Intel - 32nm, 22nm, 15nm, Defect Densities, Hi-K, Strained Silicon & Billions of Transistors
Annexure :

Mark Bohr needs little introduction. He is an Intel Senior Fellow and Director of Process Architecture and Integration. This video starts with a discussion of how Intel's 45nm production ramp is going. The first year of the 45nm ramp was twice as fast as the 65nm ramp and defect densities are the lowest for any Intel technology ever. You'll also find out the answer to the question many want to know: are there any problems with high-k metal gate?

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