Mark Bohr, Intel Fellow and Dir. of Process Arch. and Int., discusses process technology development on Intel's 65nm Process in this 2003 interview. Topics covered include: Strained Silicon process, Hi-k metal gate, and having achieved working SRAM cells on its C5 process. It marks the first fully integrated 65nm process flow. The process was a fully featured process for MPUs including copper interconnect, second generation strained silicon, and HKMG. Technology reuse from 90nm, including new mask making technology to extend their lithography tools for capital efficiency, developed at their internal mask shop. The challenge of introducing Alternating Phase Shift masks to manufacturing. The benefit of having an in-house mask shop and how much they make versus have made by merchant mask shops. Their newest 300mm development fab D1D is described.